VLSI Designer (2-6 Years)

Posted on 01-Nov-2017 by : Aricent Technologies Limited
Chennai
Not Disclosed
Full-Time

Keyskills : Financial Analysis VLSI


Job Summary

14 Openings
IT-software services
IT/ Software/ Services
Graduation

Job Description

  • Experience in taking the design through P&R from Netlist to GDS including timing closure and Physical verification (Proficient in Synopsys ICC, Magma Talus or Cadence FE tool set.).
  • Proficient in Synopsys ICC, Magma Talus or Cadence FE tool set. Experience with Mentor Olympus tool is a Plus Knowledge of I /R drop analysis is a Plus Excellent interpersonal and analytical skills with the ability to work independently.


Roles & Responsibilities

    • Technically contributing in following domains: Floor planning, place and route, Clock Tree Synthesis,Clock Distribution.
    • IP integration, extraction, Timing closure, Power andSignal Integrity Analysis, Physical Verification, DFM and Tape Out MandatorySkills: Hands on experience in all of the aspects of physical design including synthesis, floor planning, place and route, Clock Tree Synthesis, Clock Distribution.
    • IP integration, extraction, Timing closure, Timing ECOs, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out. 


Company Profile

Aricent is a global design and engineering company innovating in the digital era. With more than 12,000 talented designers and engineers and over 25 years of experience, we help the world's leading companies solve their most important business and technology innovation challenges - from Customer to Chip.

See other Courses

Share job on :
VLSI Design (4-9 Years)
Mistral Solutions Private Limited
Not Disclosed

Matlab Developer (3-8 Years)
Supreme Netsoft Pvt. Ltd
Not Disclosed
Keyskills : MATLAB VLSI